The use of voltage sense amplifiers with hysteresis for noise rejection is known. The simplest voltage sense amplifier is an operational amplifier in a positive feedback configuration. In the case of voltage hysteresis two different trip points (Tph and Tpl) are defined and circuits are designed such that when a high signal is to be recognized it must exhibit a voltage higher than Tph before it is recognized and declared a high signal. In a similar manner, before a low signal is recognized it must exhibit a low voltage lower than the second trip point Tpl. A simple illustration of this is provided in FIGS. 1A, 1B and 1C.
Presently, most CMOS integrated circuit interconnections rely on the transmission of a voltage step or signal from one location to another. The driver may simply be a CMOS inverter or NMOS transistor with a passive pull up load resistor and the receiver a simple CMOS amplifier, differential amplifier or comparator. The CMOS receiver presents a high impedance termination or load to the interconnection line. This fact is problematic for several identifiable reasons. For example, the high impedance termination is troublesome because the switching time response or signal delay is determined mainly by the ability of the driver to charge up the capacitance of the line and the load capacitance. Also, the interconnection line is not terminated by its characteristic impedance resulting in reflections and ringing, and large noise voltages may be induced on the signal transmission line due to capacitive coupling and large voltage switching on adjacent lines. The result is that the noise voltage can be a large fraction of the signal voltage.
The transmission of voltage step signals works well if the interconnection transmission line is short so that the stray capacitance of the line is small. However, in longer low impedance transmission lines, such as those which exist on most CMOS integrated circuits, the noise voltage presents a difficult problem. These longer low impedance transmission lines are in fact more amenable to current signaling. These longer transmission lines may be on the CMOS integrated circuit itself, an interconnection line between integrated circuits mounted in a module as for instance a memory module, an interposer upon which these integrated circuits are mounted, or on a printed circuit board upon which the integrated circuits are mounted.
In the quest for higher speed signaling it has recently been proposed to use current mode interconnections rather than voltage mode. The goal is to provide impedance matching on signal interconnection lines to reduce or avoid reflections and ringing on the lines. The technique proposed is matching termination of the signal line(s) to the signal receiver by using current mode interconnections and current mode sense amplifiers or current mode comparators. Signal interconnection and clock distribution lines with low controlled impedances are most amenable to current mode signaling. Metal lines separated from metal ground planes or metal power supply distribution planes (which are at AC ground) by oxide or other integrated circuit insulators will have low characteristic impedances of the order 50 or 75 ohms. To avoid reflections and ringing these need to be terminated in their characteristic impedance which requires sense amplifiers or receivers with low input impedances and implies small voltage swings on the lines.
Independent of whether voltage signals or current-mode signals are employed two different types of interconnections exist, the first type includes single sided/single ended interconnections and the second type includes differential interconnections. Differential interconnections are often desirable in that they reduce common mode noise. However, differential interconnections require two interconnection transmission lines and, in I/O applications, they require twice as many input/output pads and packaging pins which is a problem in some applications. The requirement of two interconnection transmission lines creates twice as much crowding on the precious chip surface area available in certain CMOS applications. Single sided/single ended pseudo differential interconnections have some of the advantages of differential interconnections, like power supply noise rejection. Single sided/single ended pseudo differential interconnections use a single transmission line interconnection.
In the "quasi-differential" amplifier, a single transmission line interconnection is utilized and one input of the voltage sense amplifier driven with a reference potential. The "quasi-differential" technique, and with voltage sensing on a terminated line has been used in 400 Mbs CMOS systems. FIG. 2 provides a schematic for a conventional "pseudo-differential" amplifier. In the "pseudo-differential" amplifier technique one side of the different type of voltage sense amplifier is driven with a combination of ground potential and a reference potential. Unfortunately, achieving high data rates is difficult with single-ended or unbalanced signal transmission lines at high frequencies because a large amount of noise is generated in the interconnection system including crosstalk and radiation in backplanes, connectors and cables.
FIG. 3 provides an illustration of the conventional differential current sense amplifier. This conventional current sense amplifier, receiving fully differential input signals, can respond more rapidly than those single ended/single sided amplifiers mentioned above. Also, the fully differential sense amplifier has lower power constraints and can be driven with a small 0.5 mA input signal on the input transmission lines. However, the conventional differential current sense amplifier is not very responsive to single sided or single ended input signals where one side, or input, is driven with a reference current signal, e.g. zero Amperes and the other input is used in an attempt to detect a current signal. When used in such a manner the response of the current sense amplifier with a single sided input is very poor. There is simply not enough gain and feedback in the positive feedback latch to result in a large output signal for a 1 milliampere (mA) input signal. Instead a larger 5 mA input signal is required which places greater power demands on the overall CMOS circuit.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop sense amplifiers which are even less susceptible to induced noise, current reflections or ringing. It is further desirable to develop low power sense amplifiers which provide rapid response times using single sided/ended inputs.